1. Field of the Invention
This invention relates generally to the field of data processing systems, and, more particularly, to cache memory used in data processing systems. Specifically, the present invention relates to a cache memory with reduced latency.
2. Description of the Related Art
The demand for quicker and more powerful personal computers has led to many technological advances in the computer industry, including the development of faster memories. Historically, the performance of a personal computer has been directly linked to the efficiency by which data can be accessed from memory, often referred to as the memory access time. Generally, the performance of a central processing unit (CPU or microprocessor), which functions at a high speed, has been hindered by slow memory access times. Therefore, to expedite the access to main memory data, cache memories have been developed for storing frequently used information.
A cache is a relatively small high-speed memory that is used to hold the contents of the most recently utilized blocks of main storage. A cache bridges the gap between fast processor cycle time and slow memory access time. Using this very fast memory, the microprocessor can reduce the number of wait states that are interposed during memory accesses. When the processor issues the load instructions to the cache, the cache checks its contents to determine if the data is present. If the data is already present in the cache (termed a "hit"), the data is forwarded to the CPU with practically no wait. If, however, the data is not present (termed a "miss"), the cache must retrieve the data from a slower, secondary memory source, which may be the main memory or another cache, in a multi-level cache memory system. In addition, the retrieved information is also copied (i.e. stored) into the cache memory so that it is readily available to the microprocessor for future use.
Most cache memories have a similar physical structure. Caches generally have two major subsystems, a tag subsystem (also referred to as a cache tag array) and memory subsystem (also known as cache data array). A tag subsystem holds the addresses and determines where there is a match for a requested datum, and a memory subsystem stores and delivers the data upon request. Thus, typically, each tag entry is associated with a data array entry, where each tag entry stores index information relating to each data array entry. Some data processing systems have several cache memories (i.e. a multi-level cache system), in which case, each data array will have a corresponding tag array to store addresses.
Utilizing a multi-level cache memory system can generally improve the proficiency of a central processing unit. In a multi-level cache infrastructure, a series of caches L0, L1, L2 can be linked together, where each cache is accessed serially by the microprocessor. For example, in a three-level cache system, the microprocessor will first access the L0 cache for data, and in case of a miss, it will access cache L1. If L1 does not contain the data, it will access the L2 cache before accessing the main memory. Since caches are typically smaller and faster than the main memory, the general trend is to design modem computers using a multi-level cache system.
Even a multi-level cache system, however, can sometimes hamper the performance of a computer because of the serial manner in which the caches in a multi-level cache system are accessed. The overall cache latency of the multi-level cache system tends to be high because each cache performs a lookup of a memory request before forwarding the memory request to the next level cache. Thus, what is needed is a method and apparatus for reducing the overall cache latency of a cache memory system.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.